7. Control and Status Registers - 2025-12-30

F-Tile Serial Lite IV IP User Guide

Version: 25.3.1

1. About the F-Tile Serial Lite IV IP User Guide
2. F-Tile Serial Lite IV IP Overview
2.1. Release Information
2.2. Supported Features
2.3. IP Version Support Level
2.4. Device Speed Grade Support
2.5. Resource Utilization and Latency
2.6. Bandwidth Efficiency
3. Getting Started
3.1. Installing and Licensing IP Cores
3.1.1. IP Evaluation Mode
3.2. Specifying the IP Parameters and Options
3.3. Generated File Structure
3.4. Simulating IP Cores
3.4.1. Simulating and Verifying the Design
3.5. Synthesizing IP Cores in Other EDA Tools
3.6. Compiling the Full Design
4. Functional Description
4.1. TX Datapath
4.1.1. TX MAC Adapter
4.1.2. Control Word (CW) Insertion
4.1.2.1. Start-of-burst CW
4.1.2.2. End-of-burst CW
4.1.2.3. Alignment Paired CW
4.1.2.4. Empty-cycle CW
4.1.2.5. Idle CW
4.1.2.6. Data Word
4.1.3. TX CRC
4.1.4. TX MII Encoder
4.1.5. TX PCS and PMA
4.2. RX Datapath
4.2.1. RX PCS and PMA
4.2.2. RX MII Decoder
4.2.3. RX CRC
4.2.4. RX Deskew
4.2.5. RX CW Removal
4.3. F-Tile Serial Lite IV IP Clock Architecture
4.4. Reset and Link Initialization
4.4.1. TX Reset and Initialization Sequence
4.4.2. RX Reset and Initialization Sequence
4.5. Link Rate and Bandwidth Efficiency Calculation
4.6. 32-bit Soft CWBIN Counters
4.7. i_stats_snapshot Port
4.8. Deterministic Latency
4.8.1. Deterministic Latency Top Wrapper
4.8.1.1. TX DL Shim Wrapper
4.8.1.2. RX DL Shim Wrapper
4.8.1.3. Deterministic Latency Design Considerations
5. Parameters
6. F-Tile Serial Lite IV IP Interface Signals
6.1. Clock Signals
6.2. Reset Signals
6.3. MAC Signals
6.4. Transceiver Reconfiguration Signals
6.5. PMA Signals
7. Control and Status Registers
7.1. F-Tile Serial Lite IV IP Soft CSR
8. Designing with F-Tile Serial Lite IV IP
8.1. Reset Guidelines
8.2. Error Handling Guidelines
8.3. Analog Parameter Settings
9. F-Tile Serial Lite IV IP User Guide Archives
10. Document Revision History for the F-Tile Serial Lite IV IP User Guide

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