| 2025.10.25 |
25.3 |
8.1.4 |
- Updated the recommended settings of FGT
TXEQ Main Tap and Enable FGT VSR mode parameters in Table:
Recommended Analog Settings for
FGT Designs.
- Updated Figure: Analog Parameters Tab for FGT.
- Changed IP name to F-Tile Interlaken IP.
|
| 2025.03.30 |
25.1 |
8.1.3 |
Added Agilex 7 FPGA I-Series
Transceiver-SoC Development Kit (Production 2 4x F-Tiles) |
| 2024.09.30 |
24.3 |
8.1.1 |
Added Device Initialization Clock tab to
Example Design tab in
GUI |
| 2024.07.08 |
24.2 |
8.1.0 |
- Updated Recommended Analog Settings for FGT Designs
table
- Updated Reset
Sequence in NRZ Mode figure.
- Updated Reset
Sequence in PAM4 Mode figure.
|
| 2023.12.04 |
23.4 |
8.0.0 |
- Updated the Quartus version and IP
version.
- Updated Table 1: Supported Combinations of
Number of Lanes and Data Rates.
- Added support for Questa*-Intel® FPGA Edition
simulator.
|
| 2023.10.02 |
23.3 |
7.1.0 |
Added a new section named Analog Parameters
Settings. |
| 2023.06.26 |
23.2 |
7.0.0 |
- Updated the figure Example Design
Tab.
- Updated step 9 of the Generating the
Design section.
- Updated the Note at the beginning of the
Register Map section.
|
| 2023.04.11 |
23.1 |
6.1.0 |
- Updated the product family name to "Intel
Agilex 7."
-
Register Map: New register information
"fec_snapshot" added in the following tables:
-
Design
Example Register Map
-
Design
Example Register Map for Interlaken Look-aside
Design Example
|
| 2022.12.22 |
22.4 |
6.0.0 |
-
Quick Start
Guide: IP Supported
Combinations of Number of Lanes and Data
Rates table updated
-
Generating the
Design: Note added about VSR mode setting at
the end of the section
-
Compiling and
Configuring the Hardware Design Example:
Minor corrections in Step 4(b). PAM changed to PAM4.
166.66 MHz changed to 156.25 MHz
-
Testing the
Hardware Design Example: Note added in Step
4(c)
|
| 2022.09.26 |
22.3 |
5.0.0 |
- Updated the development kit device part
numbers in section: Generating the
Design.
- Updated the Figure: Directory Structure.
- Updated the steps in section: Compiling and Configuring the Hardware
Design Example.
- Added the external serial loopback support
for FHT PMA.
- Updated the section: Interface Signals with:
-
pll_ref_clk signal description
- New signals:
-
systempll_ref_clk
-
tx_fc_clk
-
tx_fc_data
-
tx_fc_sync
-
rx_fc_clk
-
rx_fc_data
-
rx_fc_sync
|
| 2022.06.21 |
22.2 |
4.1.0 |
- Added the FHT PMA support for PAM4
variants.
- Updated commands in section: Testing the Hardware Design
Example.
|
| 2022.03.28 |
22.1 |
4.0.0 |
- Added support for the Interlaken
Look-aside mode for all variants.
- Removed support for the
ModelSim®
SE
simulator.
|
| 2022.01.14 |
21.4 |
3.1.0 |
- Added support for the Cadence*
Xcelium™
simulator.
- Added support for the Interlaken
Look-aside mode for three variants:
- 6 x 53.125G
- 12 x 12.5G
- 12 x 25.78125G
- Added hardware support for the F-tile
Interlaken
Intel®
FPGA IP Design Example.
|
| 2021.10.04 |
21.3 |
3.0.0 |
- Added support for new lane rate
combinations. For more information, refer to Table: IP Supported Combinations of
Number of Lanes and Data Rate.
- Updated the supported simulator list in
section: Hardware and Software
Requirements.
- Added new reset registers in section:
Register Map.
|
| 2021.06.21 |
21.2 |
2.0.0 |
Initial release. |