1.3. Directory Structure - 2025-12-16

F-Tile Interlaken IP Design Example User Guide
Version
25.3
Product Type
Device Families > Agilex Families > Agilex 7 > M-Series
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Agilex Families > Agilex 7
Device Families > Agilex Families > Agilex 7 > I-Series
Resource Type
Documentation > User Guides
ft:sourceName
DITA
The F-Tile Interlaken IP core generates the following files for the design example:
Figure 5. Directory Structure
Table 2.  Hardware Design Example File DescriptionsThese files are in the <design_example_installation_dir>/ilk_f_0_example_design directory.
File Names Description
example_design.qpf Quartus® Prime project file.
example_design.qsf Quartus® Prime project settings file
example_design.sdc

jtag_timing_template.sdc

Synopsys® Design Constraint file. You can copy and modify for your own design.
sysconsole_testbench.tcl Main file for accessing System Console.

File location: <design_example_installation_dir>/ilk_f_0_example_design/example_design/hwtest

Table 3.  Testbench File DescriptionThis file is in the <design_example_installation_dir>/ilk_f_0_example_design/example_design/rtl directory.
File Name Description
top_tb.sv Top-level testbench file.
Table 4.  Testbench ScriptsThese files are in the <design_example_installation_dir>/ilk_f_0_example_design/example_design/testbench directory.
File Name Description
run_vcs.sh The Synopsys® VCS® script to run the testbench.
run_vcsmx.sh The Synopsys® VCS® MX script to run the testbench.
run_mentor.tcl The Siemens® EDA QuestaSIM® script to run the testbench.
run_xcelium.sh The Cadence* Xcelium™ script to run the testbench.