1.5. Compiling and Configuring the Hardware Design Example

Ensure the example design generation is complete.
In the Quartus^® Prime Pro Edition software, open the Quartus^® Prime project <design_example_installation_dir>/example_design.qpf>.
On the Processing menu, click Start Compilation.
After successful compilation, a .sof file is available in your specified directory. Follow these steps to program the hardware example design on the Agilex™ 7 device with F-tile:
1. Connect the Development Kit to the host computer.
2. Launch the Clock Control application, which is part of the development kit. Set new frequencies for the design example as following:
  - For NRZ mode:
    - Si5391-A (U18), OUT0: Set to the value of pll_ref_clk ² to 156.25 MHz.
    - Si5332 (U19), OUT6: Set to the value of mgmt_clk ² to 100 MHz.
  - For PAM4 mode:
    - Si5391-B (U45), OUT1: Set to the value of pll_ref_clk ² to 156.25 MHz.
    - Si5332 (U19), OUT1: Set to the value of mac_pll_ref_clk ² to 156.25 MHz.
    - Si5332 (U19), OUT6: Set to the value of mgmt_clk ² to 100 MHz.
    - For FHT or when EFIFO is enabled:
      
      Si5394 (U118), OUT3: Set to the value of systempll_ref_clk ² per your design requirement.
3. Click Tools > Programmer > Hardware Setup.
4. Select a programming device. Add the Agilex™ 7 I-Series Transceiver-SoC Development Kit.
5. Ensure that Mode is set to JTAG.
6. Select the Agilex™ 7 I-Series device and click Add Device. The programmer displays a diagram of the connections between the devices on your board.
7. Check the box for the .sof.
8. Check the box in the Program/Configure column.
9. Click Start.

² The Clock Control GUI application cannot drive all the frequencies.

1.5. Compiling and Configuring the Hardware Design Example - 2025-12-16

F-Tile Interlaken IP Design Example User Guide