AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY - This application note provides design examples demonstrating scalable 10G Ethernet MAC using 1G/10G PHY. - 2016-05-13

1. Scalable 10G Ethernet MAC using 1G/10G PHY
1.1. Features
1.2. Parameters
1.3. Block Diagrams
1.4. Components
1.5. Requirements
1.6. Design Example Walkthrough
1.6.1. Setting Up the Design Examples
1.6.2. Changing Number of Channels
1.6.3. Configuring PHY Speed
1.6.3.1. Changing Speed between 10G and 1G in 1000BaseX mode
1.6.3.2. Changing Speed between 1G, 100M, and 10M SGMII
1.6.4. IP Regeneration
1.7. Design Example Testbench
1.7.1. Testbench Components
1.7.2. Testbench Files
1.7.3. Simulating Testbench
1.7.3.1. Using ModelSim Simulator
1.7.3.2. Using VCS Simulator
1.7.4. Test Case
1.7.4.1. Test Scenario for Design Example without IEEE 1588v2
1.7.4.2. Test Scenario for Design Example with IEEE 1588v2
1.7.4.2.1. Testcase 1
1.7.4.2.2. Testcase 2
1.7.4.2.3. Testcase 3
1.8. Clocking Scheme
1.8.1. Clocking Diagram
1.8.2. Sync-E Support
1.8.2.1. Enable Ref Clock Sharing
1.8.2.2. Disable Ref Clock Sharing
1.9. Reset Scheme
1.9.1. Design Example without IEEE 1588v2
1.9.1.1. Channel Level Reset Scheme
1.9.1.2. Multi-Channel Level Reset Scheme
1.9.2. Design Example with IEEE 1588v2
1.9.2.1. Channel Level Reset Scheme
1.9.2.2. Multi-Channel Level Reset Scheme
1.9.3. Internal PHY PLL Powerdown Connection Scheme
1.10. Interface Signals
1.10.1. Clock and Reset Interface Signals
1.10.2. Avalon-MM Interface Signals
1.10.3. Avalon-ST Interface Signals
1.10.4. PHY Interface Signals
1.10.5. MDIO Interface Signals
1.10.6. IEEE 1588v2 Timestamp Interface Signals
1.10.7. Packet Classifier Interface Signals
1.10.8. ToD Interface Signals
1.11. Register Map
1.11.1. Master TOD
1.11.2. 1G TOD
1.11.3. 10G TOD
1.11.4. PHY
1.11.5. 1G/10G MAC
1.12. Known Issues
1.13. Document Revision History

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