LVDS SERDES Transmitter / Receiver IP Cores User Guide - 2017-12-15

Version: 17.1

1. LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.1. Features
1.1.1. Resource Utilization and Performance
1.2. Parameter Settings
1.2.1. ALTLVDS_TX Parameter Settings
1.2.2. ALTLVDS_RX Parameter Settings
1.2.3. Command Line Interface Parameters
1.3. Ports
1.3.1. ALTLVDS_TX Ports
1.3.2. ALTLVDS_RX Ports
1.4. Prototypes and Component Declarations
1.4.1. Verilog HDL Prototype
1.4.2. VHDL Component Declaration
1.4.3. VHDL LIBRARY-USE Declaration
1.5. Functional Description
1.5.1. Receiver Modes
1.5.1.1. DPA Mode
1.5.1.2. Non-DPA Mode
1.5.1.3. Soft-CDR Mode
1.5.1.3.1. Clock Forwarding
1.5.1.3.2. Standard Mode
1.5.1.3.3. No Output Register Mode
1.5.2. DPA PLL Calibration
1.5.2.1. DPA PLL Calibration in Stratix IV ES Devices
1.5.2.2. DPA PLL Calibration in Arria II and Stratix IV Devices and Later
1.5.2.3. Effects of DPA PLL Calibration
1.5.3. Initialization and Reset
1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX
1.5.3.2. Resetting the DPA
1.5.3.3. Aligning the Word Boundaries
1.5.3.4. Recommended Initialization and Reset Flow
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints
1.5.4.1. Dedicated SERDES
1.5.4.2. SERDES in LEs
1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew
1.5.4.3.1. Obtaining the RSKM Report
1.5.4.3.2. Obtaining the TCCS Report
1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI
1.5.4.4.1. Constraining the Input Clock Signal
1.5.4.4.1.1. Constraining the Synchronous Input Ports
1.5.4.4.1.2. Setting False Path for the Asynchronous Input and Output Ports
1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File
1.5.5. Arria II GX, Arria V, Arria V GZ, Cyclone V, and Stratix V LVDS Package Skew Compensation Report Panel
1.5.6. ALTLVDS IP Core in External PLL Mode
1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode
1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
1.6. Simulating Intel FPGA IP Cores
1.7. Generating ALTLVDS IP Core Using Clear Box Generator
1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives
1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide

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