AN 833: Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design - 2017-12-19

Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Reference Design Block Diagram
Key Features
Submodules in the Top-Level HDL Files
Requirements
Hardware Requirements
Software Requirements
Reference Design Walkthrough
Hardware Set Up
Running the Reference Design
Compiling the Project to Include Signal Tap II File
Setting Up the TI ADC12DJxx00 GUI Software and Board
Configuring the FPGA
Checking the Basic Operation
Executing the .tcl Code and Initializing the JESD204B Links
Checking the Deterministic Latency
Viewing the Results
Link Up Test Results
Short Transport Layer and Ramp Test Mode Test Results
Verifying Short Transport Test Patterns at Receiver Transport Layer
Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Deterministic Latency Test Results
Rebuilding Design
Procedures in the main.tcl System Console Script
Document Revision History for AN 833: Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

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