MAX 10 Clocking and PLL User Guide - Describes the Intel MAX 10 device clock networks, internal oscillator, and PLLs for clock management and synthesis. - 2021-11-01

Version: 21.1

1. Intel MAX 10 Clocking and PLL Overview
1.1. Clock Networks Overview
1.2. Internal Oscillator Overview
1.3. PLLs Overview
2. Intel MAX 10 Clocking and PLL Architecture and Features
2.1. Clock Networks Architecture and Features
2.1.1. Global Clock Networks
2.1.2. Clock Pins Introduction
2.1.3. Clock Resources
2.1.4. Global Clock Network Sources
2.1.5. Global Clock Control Block
2.1.6. Global Clock Network Power Down
2.1.7. Clock Enable Signals
2.2. Internal Oscillator Architecture and Features
2.3. PLLs Architecture and Features
2.3.1. PLL Architecture
2.3.2. PLL Features
2.3.3. PLL Locations
2.3.4. Clock Pin to PLL Connections
2.3.5. PLL Counter to GCLK Connections
2.3.6. PLL Control Signals
2.3.7. Clock Feedback Modes
2.3.7.1. Source Synchronous Mode
2.3.7.2. No Compensation Mode
2.3.7.3. Normal Mode
2.3.7.4. Zero-Delay Buffer Mode
2.3.8. PLL External Clock Output
2.3.9. ADC Clock Input from PLL
2.3.10. Spread-Spectrum Clocking
2.3.11. PLL Programmable Parameters
2.3.11.1. Programmable Duty Cycle
2.3.11.2. Programmable Bandwidth
2.3.11.3. Programmable Phase Shift
2.3.12. Clock Switchover
2.3.12.1. Automatic Clock Switchover
2.3.12.2. Automatic Switchover with Manual Override
2.3.12.3. Manual Clock Switchover
2.3.13. PLL Cascading
2.3.13.1. PLL-to-PLL Cascading
2.3.13.2. Counter-to-Counter Cascading
2.3.14. PLL Reconfiguration
3. Intel MAX 10 Clocking and PLL Design Considerations
3.1. Clock Networks Design Considerations
3.1.1. Guideline: Clock Enable Signals
3.1.2. Guideline: Connectivity Restrictions
3.2. Internal Oscillator Design Considerations
3.2.1. Guideline: Connectivity Restrictions
3.3. PLLs Design Considerations
3.3.1. Guideline: PLL Control Signals
3.3.2. Guideline: Connectivity Restrictions
3.3.3. Guideline: Self-Reset
3.3.4. Guideline: Output Clocks
3.3.5. Guideline: PLL Cascading
3.3.6. Guideline: Clock Switchover
3.3.7. Guideline: .mif Streaming in PLL Reconfiguration
3.3.8. Guideline: scandone Signal for PLL Reconfiguration
4. Intel MAX 10 Clocking and PLL Implementation Guides
4.1. ALTCLKCTRL Intel FPGA IP Core
4.2. ALTPLL Intel FPGA IP Core
4.2.1. Expanding the PLL Lock Range
4.2.2. Programmable Bandwidth with Advanced Parameters
4.2.3. PLL Dynamic Reconfiguration Implementation
4.2.3.1. Post-Scale Counters (C0 to C4)
4.2.3.2. Scan Chain
4.2.3.3. Charge Pump and Loop Filter
4.2.3.4. Bypassing PLL Counter
4.2.4. Dynamic Phase Configuration Implementation
4.2.4.1. Dynamic Phase Configuration Counter Selection
4.2.4.2. Dynamic Phase Configuration with Advanced Parameters
4.3. ALTPLL_RECONFIG Intel FPGA IP Core
4.3.1. Obtaining the Resource Utilization Report
4.4. Internal Oscillator Intel FPGA IP Core
5. ALTCLKCTRL Intel FPGA IP Core References
5.1. ALTCLKCTRL IP Core Parameters
5.2. ALTCLKCTRL IP Core Ports and Signals
6. ALTPLL Intel FPGA IP Core References
6.1. ALTPLL IP Core Parameters
6.1.1. Operation Modes Parameter Settings
6.1.2. PLL Control Signals Parameter Settings
6.1.3. Programmable Bandwidth Parameter Settings
6.1.4. Clock Switchover Parameter Settings
6.1.5. PLL Dynamic Reconfiguration Parameter Settings
6.1.6. Dynamic Phase Configuration Parameter Settings
6.1.7. Output Clocks Parameter Settings
6.2. ALTPLL IP Core Ports and Signals
7. ALTPLL_RECONFIG Intel FPGA IP Core References
7.1. ALTPLL_RECONFIG IP Core Parameters
7.2. ALTPLL_RECONFIG IP Core Ports and Signals
7.3. ALTPLL_RECONFIG IP Core Counter Settings
8. Internal Oscillator Intel FPGA IP Core References
8.1. Internal Oscillator IP Core Parameters
8.2. Internal Oscillator IP Core Ports and Signals
9. Intel MAX 10 Clocking and PLL User Guide Archives
10. Document Revision History for the Intel MAX 10 Clocking and PLL User Guide

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