Using Quartus® Prime software, you can generate a programmed I/O (PIO) design example for the Intel® FPGA P-Tile Avalon® -ST Hard IP for PCI Express® IP core. The generated design example reflects the parameters that you specify. The PIO example transfers data from a host processor to a target device. It is appropriate for low-bandwidth applications. This design example automatically creates the files necessary to simulate and compile in the Quartus® Prime software. You can download the compiled design to your FPGA Development Board. To download to custom hardware, update the Quartus® Prime Settings File (.qsf) with the correct pin assignments .
Figure 11. Development Steps for the Design Example