| 2024.04.04 |
24.1 |
9.1.1 |
Removed mentions of support for the
Agilex™ 7 F-Series P-Tile
ES0 FPGA Development Kit from the Overview, Generating the Design
Example, and Compiling the Design Example sections. |
| 2023.10.02 |
23.3 |
9.0.3 |
Updated the instructions in the Running
Simulations Using
QuestaSim®
section. |
| 2023.06.26 |
23.2 |
9.0.2 |
Updated the IP version number. |
| 2023.04.10 |
23.1 |
9.0.1 |
- Updated the product family name to
Agilex™ 7.
- Updated the simulation commands in the Running simulations Using VCS section.
|
| 2022.12.19 |
22.4 |
9.0.0 |
- Added a Note to the Simulating the
Design Example section stating that QuestaSim 2022.3 is required to run
simulations from
Quartus® Prime 22.3 onward.
- Updated the simulation command for VCS in the Simulating the Design Example section.
|
| 2022.09.26 |
22.3 |
8.3.0 |
- Updated the instructions in the Running the Performance Design Example section to include the step for
choosing the payload size for DMA operations.
- Updated the Running the SR-IOV Design
Example section to include sample enumeration results of running an
SR-IOV design example with multiple PFs and VFs.
|
| 2022.06.20 |
22.2 |
8.1.0 |
- Added support for Gen3 x8 and Gen4 x8 modes to the PIO design
example.
- Removed support for the
Stratix® 10 DX ES1 FPGA Development Kit from the Generating the Design Example section.
|
| 2022.03.28 |
22.1 |
8.0.0 |
- Added the section Overview to
describe the simulation and hardware testing support for all the design
examples.
- Added instructions on how to run the Riviera* simulator to the
Simulating the Design Example section.
- Added the section Running the
Performance Design Example.
- Added a note to the Running the Design
Example section stating that the refclk switch on the
Stratix® 10 DX FPGA Development Kit or the
Agilex
FPGA Development Kit must be set to the OFF position to select the common refclk
from the PCIe Edge Connector for PCIe link stability.
|
| 2021.12.15 |
21.4 |
7.0.0 |
- Added the section Hardware and
Software Requirements.
- Added the description for the Performance design example to
the Design Example Description section.
- Added steps to generate the Performance design example to the
Generating the Design Example section.
- Added the description for the Performance design example
testbench to the Simulating the Design Example
section.
|
| 2021.10.04 |
21.3 |
6.0.0 |
- Changed the supported configurations for the SR-IOV design
example from Gen3 x16 EP and Gen4 x16 EP to Gen3 x8 EP and Gen4 x8 EP in the Functional Description for the Single Root I/O Virtualization
(SR-IOV) Design Example section.
- Added the support for the
Stratix® 10 DX P-tile Production FPGA Development Kit to the Generating the Design Example section.
|
| 2021.07.01 |
21.2 |
5.0.0 |
- Removed the simulation waveforms for the PIO and SR-IOV design
examples from the section Simulating the Design
Example.
- Updated the command to display the BDF in the section Running the PIO Design Example.
|
| 2020.10.05 |
20.3 |
3.1.0 |
Removed the Registers section since the Avalon Streaming design examples have no control
register. |
| 2020.07.10 |
20.2 |
3.0.0 |
- Added simulation waveforms, test case descriptions and test
result descriptions for the design examples.
- Added simulation instructions for the ModelSim simulator to
the Simulating the Design Example section.
|
| 2020.05.07 |
20.1 |
2.0.0 |
- Updated the document title to P-Tile
Avalon®
streaming IP for
PCI Express®
Design Example User Guide to
meet new legal naming guidelines.
- Updated the VCS interactive mode simulation command.
|
| 2019.12.16 |
19.4 |
1.1.0 |
Added SR-IOV design example description. |
| 2019.11.13 |
19.3 |
1.0.0 |
Added Gen4 x8 Endpoint and Gen3 x8 Endpoint to
the list of supported configurations. |
| 2019.05.03 |
19.1.1 |
1.0.0 |
Initial release. |