2.1. Directory Structure - 2025-12-15

P-Tile Avalon Streaming IP for PCI Express Design Example User Guide

Version: 24.1

1. About the P-tile Avalon Streaming Intel FPGA IP for PCI Express Design Examples
1.1. Overview
1.2. Functional Description for the Programmed Input/Output (PIO) Design Example
1.3. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example
1.4. Functional Description for the Performance Design Example
1.5. Hardware and Software Requirements
2. Quick Start Guide
2.1. Directory Structure
2.2. Generating the Design Example
2.3. Simulating the Design Example
2.3.1. Steps to Run Simulations
2.3.1.1. Running Simulations Using QuestaSim*
2.3.1.2. Running Simulations Using VCS*
2.3.1.3. Running Simulations Using Riviera*
2.3.2. Testbench
2.3.2.1. Test Driver Module
2.3.2.2. PIO Design Example Testbench
2.3.2.3. SR-IOV Design Example Testbench
2.3.2.4. Performance Design Example Testbench
2.4. Compiling the Design Example
2.5. Installing the Linux Kernel Driver
2.6. Running the Design Example
2.6.1. Running the PIO Design Example
2.6.2. Running the SR-IOV Design Example
2.6.3. Running the Performance Design Example
3. P-tile Avalon Streaming IP for PCI Express Design Example User Guide Archives
4. Document Revision History for the Intel P-Tile Avalon Streaming Hard IP for PCIe Design Example User Guide

Figure 12. Directory Structure for the Generated Design Example

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