The Support-Logic Generation is a pre-synthesis step used to
generate tile-related files needed for simulation and hardware design. The tile generation is
a required step before simulation.
You can use the Support-Logic Generation command on the Processing menu in the Quartus® Prime Pro Edition software to generate the F-Tile specific files your design. Alternatively, you can run quartus_tlg command prompt to generate these files.
Starting with the Quartus® Prime software version 21.4, the Support-Logic Generation command is run automatically when you generate your design using F-Tile Ethernet Hard IP Example Design IP Parameter Editor.
A successful tile file generation results in the eth_f_hw_auto_tiles.x files where x represents necessary file extensions. The generated files are located in your project directory and contain the full netlist for simulation and synthesis.