4.2. F-Tile Ethernet Hard IP MAC - 2026-01-06

F-Tile Ethernet Hard IP User Guide

Version: 25.1.1

1. Overview
1.1. Ethernet System in F-Tile Overview
1.2. F-Tile Ethernet Hard IP Overview
1.2.1. Device Family Support
1.2.2. Device Speed Grade Support
1.2.3. Resource Utilization
1.2.4. Round-trip Latency
1.2.5. Release Information
2. Getting Started
2.1. Installing and Licensing F-Tile Ethernet Hard IP Cores
2.2. Specifying the IP Core Parameters and Options
2.3. Reference and System PLL Clock for your IP Design
2.4. Generated File Structure
2.4.1. Generating IP-XACT File
2.5. Generating Tile Files
2.6. IP Core Testbenches
3. F-Tile Ethernet Hard IP Parameters
4. Functional Description
4.1. Datapath Description
4.2. F-Tile Ethernet Hard IP MAC
4.2.1. MAC TX Datapath
4.2.1.1. TX Preamble, Start, and SFD Insertion
4.2.1.2. Source Address Insertion
4.2.1.3. Length/Type Field Processing
4.2.1.4. Frame Padding
4.2.1.5. Frame Check Sequence (CRC-32) Insertion
4.2.1.6. Inter-Packet Gap Generation and Insertion
4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath
4.2.2.1. RX Preamble Processing
4.2.2.2. RX Strict SFD Checking
4.2.2.3. RX FCS Checking
4.2.2.4. RX Malformed Packet Handling
4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames
4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors
4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC)
4.2.3.1. Conditions Triggering XOFF Frame Transmission
4.2.3.2. Conditions Triggering XON Frame Transmission
4.2.3.3. Pause Control and Generation Interface
4.2.3.4. Pause Control Frame Filtering
4.2.4. Link Fault Signaling
4.2.5. Order of Ethernet Transmission
4.3. PCS, OTN, and FlexE Modes
4.3.1. PCS Mode
4.3.2. OTN Mode
4.3.3. FlexE Mode
4.4. Precision Time Protocol
4.4.1. Features
4.4.2. PTP Timestamp Accuracy
4.4.3. PTP Client Flow
4.4.3.1. PTP TX Client Flow
4.4.3.2. PTP RX Client Flow
4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants
4.4.5. Virtual Lane Order and Offset Values
4.4.6. UI Adjustment
4.4.6.1. TX UI Adjustment
4.4.6.2. RX UI Adjustment
4.4.7. Reference Time Interval
4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
4.4.9. UI Value and PMA Delay
4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
4.4.11. Routing Delay Adjustment for Basic Timestamp Accuracy Mode
4.5. Auto-Negotiation and Link Training
5. Clocks
5.1. Clock Connections in Single Instance Operation
5.2. Clock Connections in Multiple Instance Operation
5.3. Clock Connections in MAC Asynchronous FIFO Operation
5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation
5.5. Clock Connections in Synchronous Ethernet Operation
5.6. Custom Cadence
6. Resets
6.1. Reset Signals
6.2. Reset Sequence
7. Interface Overview
7.1. Status Interface
7.2. TX MAC Avalon ST Client Interface
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough
7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough
7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion
7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough
7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding
7.3.3. RX MAC Adapter Limitations
7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough
7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough
7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion
7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough
7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding
7.5.3. RX MAC Segmented Client Interface Status and Errors
7.6. MAC Flow Control Interface
7.7. PCS Mode TX Interface
7.8. PCS Mode RX Interface
7.9. FlexE and OTN Mode TX Interface
7.10. FlexE and OTN Mode RX Interface
7.11. Custom Rate Interface
7.12. 32-bit Soft CWBIN Counters
7.13. Reconfiguration Interfaces
7.13.1. Ethernet Reconfiguration Interfaces
7.13.2. Transceiver Reconfiguration Interfaces
7.14. Precision Time Protocol Interface
7.14.1. Time-of-Day Interface
7.14.2. TX 2-Step Timestamp Interface
7.14.3. TX 1-Step Timestamp Interface
7.14.3.1. PTP Field Offset for 1-Step Operation
7.14.4. RX Timestamp Interface
7.14.5. PTP Status Interface
7.14.6. PTP Tile Interface
7.15. Auto-Negotiation and Link Training Interface
8. Configuration Registers
8.1. Ethernet Avalon Memory-Mapped Interface Address Space
8.1.1. Ethernet Hard IP Core CSRs
8.1.2. FEC and Transceiver Control and Status Registers
8.2. Transceiver Avalon Memory-Mapped Interface Address Space
9. Supported Modules and IPs
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet IP
9.1.1. Overview
9.1.2. Release Information
9.1.3. Functional Description
9.1.3.1. Implementing Dynamic AN/LT Solution for Separate Ethernet IPs
9.1.4. Parameters
9.1.5. Clocks and Resets
9.1.6. Registers
9.1.7. Switching between Copper Cable (DAC) and Optical Cable (AOC)
9.1.7.1. Sequence to switch from DAC to AOC
9.1.7.2. Sequence to switch back from AOC to DAC
9.1.7.3. Resetting the AN/LT Controller
9.2. PTP Tile Adapter
9.2.1. Overview
9.2.2. Clocks, Reset, and Interface Ports
9.2.3. PTP Asymmetry Delay Reconfiguration Interface
9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools
10.1. F-Tile Channel Placement Tool
10.2. Ethernet Toolkit Overview
10.2.1. Features
11. F-Tile Ethernet Hard IP User Guide Archives
12. Document Revision History for the F-Tile Ethernet Hard IP User Guide

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