12. Document Revision History for the F-Tile Ethernet Hard IP User Guide - 2026-01-06

F-Tile Ethernet Hard IP User Guide
Version
25.1.1
Document Version Quartus® Prime Version Changes
2026.01.06 25.1.1 Made the following changes:
  • Clarified the steps in TX MAC Segmented Client Interface with Disabled Preamble Passthrough for the bit order for the TX MAC segmented client interface.
2025.08.18 25.1.1 Made the following changes:
  • Added a note for the following FEC modes in the Advanced mode parameter under Parameters:
    • Fibre channel is not supported when AN/LT is enabled.
    • Ethernet Technology Consortium RS(528, 514): You cannot enable PTP in Advanced Mode.
  • Added a new parameter Advertise RS-FEC-Int Request in F-Tile Auto-Negotiation and Link Training for Ethernet IP Parameters: IP Tab.
  • Added a note in the i_reset port description in Clocks and Resets.
  • Added requirement to provide a valid PMA reference clock to the F-Tile Ethernet IP before starting AN/LT for proper operation of the F-Tile AN/LT IP in F-Tile AN/LT IP Functional Description.
  • Updated the description for the o_tx_mac_ready signal.
  • Added a note: Do not assert or de-assert TX/RX resets during AN/LT progress if enabled (register 0x3c0 value >0x60 or <0x1E0) in Resets.
  • Added a new topic: Auto-Negotiation and Link Training Interface in Interface Overview under Precision Time Protocol Interface.
  • Added a new topic: Implementing Dynamic AN/LT Solution for separate Ethernet IPs under Supported Modules and IPs Functional Description.
  • Added the following topics in Supported Modules and IPs:
    • Switching between Copper Cable (DAC) and Optical Cable (AOC)
    • Sequence to switch from DAC to AOC
    • Sequence to switch back from AOC to DAC
    • Resetting the AN/LT Controller
2025.05.30 24.3.1 Made the following changes:
  • Removed the following note description from the AN Channel location<n> parameter:
    • When Enable Dynamic AN/LT is set, only AN_CHAN = 0 is supported for all multi-lane designs.
  • Updated Enable Dynamic AN/LT note description.
  • Added the following parameters in the F-Tile AN/LT for Ethernet Intel FPGA IP Parameters: IP Tab:
    • Enable Optimized Simulation
    • Skip CPI Arbitration
2025.04.11 24.3.1 Made the following changes:
  • Updated the following in the Overview topic:
    • FEC types in the Variant Selection table
    • Added CL119 column and it's supported rates under FEC selection column
    • Updated CL91 supported rates
    • Updated CL134 supported rates
    • Added CL161 column and footnote.
  • Updated the PTP Timestamp Accuracy topic to include 10GE support and added the TOD Clock and TOD Connections in 25GE-400GE Basic Accuracy Mode diagram.
  • Updated the Reference Time Interval table to add a new row CL134, specifically for the 25GE Ethernet mode.
  • Updated the Minimum and Maximum Reference Time (TAM) Interval Allowed for UI Measurement (Hardware Basic Mode) table to add a new row CL134, specifically for the 25GE-1 Ethernet mode.
  • Updated the Minimum and Maximum Reference Time (TAM) Interval Allowed for UI Measurement (Hardware Advanced Mode) table to add a new row CL134, specifically for the 25GE-1 Ethernet mode.
  • Fixed the following typos in the Signals of the TX MAC Segmented Client Interface topic.
    • Fixed the typo in the description for the signal name i_tx_mac_valid in the Signals of the TX MAC Segmented Client Interface table.
    • Corrected i_tx_mac_frame to i_tx_mac_inframe.
2025.01.23 24.3.1 Made the following changes:
  • Updated Reset Signals topic.
  • Added the following under System Considerations in Reset Sequence.
    • The TX and RX statistics counters are cleared with CSR registers, as well as with the respective datapath resets.
    • Pulling the cable or losing CDR lock (RX down) triggers an RX datapath reset (equivalent to i_rx_rst_n).
    • Expect the initial reset acknowledgments to be asserted even without asserting the hard resets.
  • Updated the bullet description of the i_tx_mac_eop_empty and i_tx_mac_inframe signals in the TX MAC Segmented Client Interface.
  • Corrected the following typo in o_rx_mac_inframe description:
    • Indicates the number of empty bytes on the RX data signal, starting from the most significant byte (MSB). Valid only on EOP segments.
2024.11.20 24.3 Made the following changes:
  • Updated step 4 about calculating occupancy values for PTP in the RX Virtual Lane Offset Calculation for No FEC Variants.
  • Corrected [7:0] to SFD and [63:56] to the Start of Packet control byte in the figure Byte Order on the Avalon Streaming Interface Lanes With Preamble Pass-Through in the Order of Ethernet Transmission.
  • Corrected the latency from o_tx_mac_ready to i_tx_mac_valid is 1-7 clock cycles in TX Max Segmented Client Interface.
  • Corrected i_tx_mac_data to o_rx_mac_data and i_tx_mac_inframe to o_rx_mac_inframe in RX MAC Segmented Client Interface.
  • Added the following tables in PCS Mode TX Interface.
    • Alignment Marker Insertion Periods
    • Alignment Marker Insertion Periods for Simulation with Non-PTP Enabled Modes
    • Alignment Marker Insertion Periods for Simulation with PTP Enabled modes
  • Updated step 2 in PTP RX Client Flow.
  • Added port_state signal to the AN/LT IP when DR is selected in the Base IP port connections table of the Clocks and Resets section.
2024.07.08 24.2 Made the following changes:
  • Removed the following conflicting and confusing statement from TX MAC Segmented Client Interface.
    • The i_tx_mac_valid may go low during the packet transmission.
  • Updated the i_tx_mac_valid signal deasserts when the o_tx_mac_ready signal is deasserted in TX MAC Segmented Client Interface.
  • Replaced word address with Byte address for the port name i_reconfig_ptp_asym_addr[16:0] in PTP Asymmetry Delay Reconfiguration Interface.
  • Updated i_stats_snapshot signal description in the Status Signals table of Status Interface topic.
2024.06.05 24.1 Added a note that states: When a link fault occurs in the receive direction, the IP clears the RX statistic counters in Datapath Description under the Functional Description section.
2024.04.01 24.1 Made the following changes:
  • Added Agilex™ 9 device family support.
  • Updated FlexE and OTN Mode Interface topic.
  • Corrected o_tx_pll_lanes_stable to o_tx_lanes_stable in PCS Mode TX Interface.
2024.03.11 23.4 Updated the following images in Clock Connections in Synchronous Ethernet Operation.
  • Enable Dedicated CDR Clock Output IP Parameter Editor.
  • Select Designs Example Design.
2023.12.04 23.4 Made the following changes:
  • Updated resource utilization table due to changes from Nios II to Nios V.
  • Corrected the description for Stop TX traffic when link partner sends PAUSE parameter in Parameters.
  • Added new IP Parameter: Enable IPXACT in Parameters.
  • Updated TX and RX table fields for UI Value and PMA Delay of Ethernet Modes in UI Value and PMA Delay.
  • Removed the restrictions on PTP support for Agilex 7 041 devices in Device Speed Grade Support.
203.10.02 23.3 Made the following changes:
  • Corrected the i_ptp_ts_offset description and image in TX 1-Step Timestamp Interface.
  • Added F-Tile Ethernet Hard IP Parameters: IP Tab screenshot with Analog parameters tab in F-Tile Ethernet Hard IP Parameters.
  • Removed the IP Parameter: Include Deterministic Latency Interface in Parameter section.
  • Removed Deterministic latency Interface topic in Interface Overview section.
  • Added F-Tile Auto-Negotiation and Link Training for Ethernet IP parameter screenshot with Target Profile Settings tab.
  • Added the following parameters in the F-Tile Auto-Negotiation and Link Training for Ethernet IP Parameters section:
    • Enable AN/LT Debug Endpoint for Ethernet Toolkit
    • Enable Fast Simulation
    • Enable Dynamic AN/LT
2023.06.26 23.2
  • Updated alignment marker verbiage in OTN Mode.
  • Added note in PTP RX Client Flow.
  • Added description about alignment marker for the signal name i_tx_pcs66_am inSignals of the PCS66 TX Interface table.
  • Updated ANLT functional description in Supported Modules and IPs.
  • Added note under AN channel in AN/LT parameters IP tab.
  • Added a verbiage about converting byte addresses to word addresses by shifting 2 bits to the right (divide by 4) in Registers.
  • Added a note verbiage "unauthorized access to register sets outside of the configured Ethernet fractures is not recommended" in Configuration Registers.
2023.04.03 23.1
  • Updated the following in the Round-trip latency table.
    • All the IEEE 802.3 RS(544,514) replaced with IEEE 802.3 RS(528,514) (CL91).
    • All the IEEE 802.3 RS(528,514) (CL91) replaced with IEEE 802.3 RS(544,514) (CL134).
  • Added steps to retrieve the N divider value in Clock Connections in Synchronous Ethernet Operation.
  • Removed the note "Enable TX packing feature is not available when PTP is turned on" in TX Packing Logic.
  • Updated ALMs numbers in TX Packing Logic section.
  • Updated Features in Precision Time Protocol section to include 200GE and 400GE modes for timestamp accuracy in advance mode.
  • Updated 200GE and 400GE Ethernet Data Rate to ± 1.5ns for advanced accuracy mode in PTP Timestamp Accuracy.
  • Added new topic: Routing Delay Adjustment for Basic Timestamp Accuracy Mode.
  • Updated the product family name to "Intel Agilex 7."
2022.12.19 22.4 Made the following changes:
  • Updated F-Tile Ethernet Intel FPGA Hard IP Block Diagram to remove filler text in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Added the following footnotes in Variant Selection table.
    • The Auto-negotiation and link training hardware is available for no FEC, IEEE 802.3 BASE-R Firecode (CL74), and IEEE 802.3 RS(528,514) (CL91).
    • The Auto-negotiation and link training is not available for IEEE 802.3 RS(544,514) (CL134).
  • Updated note about core speed grades for IP core variation with PTP in Device Speed Grade Support.
  • Added note about only 10GE with PTP support in advanced mode for OPNs AGIB041R29D1E2VR0, AGID041R29D1E2VR0, or any device density code of 041 in Device Speed Grade Support.
  • Added new topic: Round-trip Latency in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Updated Release Information.
  • Added the following parameters:
    • Include Deterministic Latency Measurement
    • Advanced Mode
    • Custom Ethernet line rate
  • Updated Include 32-bit soft CWBIN Counters default setting to Off in Parameters.
  • Updated Enable TX packing Parameter Description in Parameters.
  • Added i_sampling_clk in Clocks.
  • Added content for Example Design Generation of Synchronous Ethernet Operation in Clock Connections in Synchronous Ethernet Operation.
  • Updated the code for calculate pulse adjustment and FEC variants in PTP RX Client Flow.
  • Added a description for i_tx_pcs66_am in FlexE and OTN Mode TX Interface.
  • Added a description for o_rx_pcs66_am_valid in FlexE and OTN Mode RX Interface.
  • Added new subsection Deterministic Latency Measurement
  • Added auto-negotiation and link training feature note in Reset Signals.
  • Added reference to Pipelined Transfers of Avalon Interface Specifications in Reconfiguration Interfaces.
2022.09.26 22.3 Made the following changes:
  • Added Core Speed Grade/Transceiver Speed Grade table in Device Speed Grade Support.
  • Updated IP-XACT file information in Generating IP-XACT File.
  • Updated F-Tile Ethernet Intel FPGA Hard IP Block Diagram to include CWBIN in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Added 32-bit soft CWBIN counters parameter description in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Updated Release Information.
  • Added Include 32bit soft CWBIN counters and Reconfig clock frequency parameters in F-Tile Ethernet Intel FPGA Hard IP Parameters.
  • Added Enable IEEE 1588 PTP parameter description "When disabled, connect this port to 1'b0" in Clock Signals table.
  • Added new topic: 32-bit Soft CWBIN Counters.
  • Added note about auto-negotiation and link training bonding support for B0 FHT multi-lane designs in AN/LT Functional Description.
  • Added new topic: Implementation of Synchronous Ethernet (syncE) operation in Clocks section.
  • Corrected o_rx_mac_status_data's value 3'd3 to reserved in RX MAC Segmented Client Interface section.
2022.06.20 22.2 Made the following changes:
  • Updated note in Device Speed Grade Support.
  • Updated the PCS Mode RX Interface section to fix Hardware AM Cycle numbers.
  • Updated the Client Flow Glossary table in PTP Client Flow section. Added a row FL-Total number of FEC lanes of the variant.
  • Added new topic: Deterministic latency Interface
  • Added new topic: TX Packing Logic.
  • Added Enable TX Packing and Include Deterministic Latency Interface parameters in F-Tile Ethernet Hard IP Parameters.
  • Fixed the broken link F-Tile Channel Placement Tool in Supported Tools.
2022.03.28 22.1 Made the following changes:
  • Updated the Variant Selection table. The Auto-negotiation and link training hardware is available for FHT NRZ 25GE-1, 50GE-2, and 100GE-4.
  • Added transceiver speed grade-related information in Device Speed Grade Support.
  • Added IP-XACT statement in Specifying the IP Core Parameters and Options.
  • Added new topic: Generating IP-XACT File
  • Updated caution note in Frame Padding to clarify 9-byte payload requirements.
  • Re-ordered step 7 and step 8 in PTP TX Client Flow.
  • Re-ordered step 9 and step 10 in PTP RX Client Flow.
  • Updated TX/RX hardware PMA delay for FHT transceivers in the UI Value and PMA Delay of Ethernet Modes table.
  • Updated the Clocks section to remove the PTP clock limitation. The PTP clock runs at 100 to 250 MHz.
  • Removed the CRC bytes statement in RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding.
  • Added reference to the .ipxact file generation in Configuration Registers.
  • Revised the i_rst_n reset description in the PTP Tile Adapter: Clocks, Reset, and Interface Ports section.
  • Removed Verilog file format specific note from the Auto-Negotiation and Link Training Parameters section. The IP supports VHDL for synthesis and simulation.
  • Updated F-Tile Ethernet Altera® FPGA Hard IP User Guide Archives.
2022.01.07 21.4 Made the following changes:
  • Updated F-Tile Ethernet Hard IP :
    • Added note about auto-negotiation and link training hardware support in Overview.
    • Added new section: Device Speed Grade Support.
    • Updated Generating Tile Files to include quartus_tlg updates.
    • Added the FHT precoding enable and Enable Native PHY Debug Endpoint parameters in the F-Tile Ethernet Hard IP Parameters.
    • Added PTP-specific i_reconfig_clk frequency range limitation.
  • Updated F-Tile Auto-Negotiation and Link Training for Ethernet IP :
    • Removed outdated 21.3 specific statement in Overview.
    • Updated Release Information.
    • Added note about VHDL limitation in F-Tile Auto-Negotiation and Link Training for Ethernet IP Parameters.
2021.10.04 21.3 Made the following changes:
  • Added support for PCS lane re-ordering in the Features table.
  • Removed 400GE-8 specific footnote from the Variant Selection table. 400GE-4 mode now supports auto-negotiation and link training.
  • Revised PTP description in F-Tile Ethernet Hard IP Overview,
  • Added Resource Utilization.
  • Updated F-Tile Ethernet Hard IP Parameters: IP Tab table:
    • Updated PMA reference frequency description.
    • Added PTP-related frequency requirements in the System PLL frequency description.
    • Added important note about hardware accuracy values in the Timestamp accuracy mode description.
    • Added new Enable Ethernet Debug Master Endpoint parameter
  • Added note in the TX MAC Segmented Client Interface.
  • Updated the TX TAM adjust calculation in PTP TX Client Flow.
  • Updated the RX TAM adjust calculation in PTP RX Client Flow.
  • Added new section: Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
  • Updated Precision Time Protocol Interface:
    • Removed 40G Ethernet rate from the PTP Clocks table. 40G Ethernet rate does not support PTP feature
    • Corrected i_clk_tx_tod clock frequency from 250 MHz to 114.2857 MHz..
  • Revised step 6 in RX UI Adjustment.
  • Update simulation-based RX TAM values for 50G Ethernet rate in Reference Time (TAM) Interval.
  • Updated Hardware UX PMA delay values in the UI Value and PMA Delay of Ethernet Modes table.
  • Globally added a note about PTP timestamp accuracy. The note emphasizes that the specified timestamp accuracy values in base and advanced modes represent simulation-based results.
  • Updated Clock Signals descriptions for the following clock signals:
    • i_clk_tx
    • i_clk_rx
    • i_clk_pll
    • i_clk_ref
  • Revised text and updated figure in Clock Connections in PTP-Based Synchronous and Asynchronous Operation.
  • Corrected signal name from i_sl_tx_valid to i_tx_valid in the TX MAC Avalon ST Client Interface.
  • Revised fixed latency range in TX MAC Segmented Client Interface. The i_tx_mac_valid and o_tx_mac_ready signals can be spaced by a fixed latency between 1 to 8 clock cycles.
  • Revised i_clk_ptp_sample clock description in the PTP Clock Ports table.
  • Added new topic: Ethernet Toolkit Overview
2021.06.28 21.2 Initial release