| Name | Description |
|---|---|
| i_clk | Clock source with 100 MHz - 250 MHz frequency. When AN/LT is enabled, i_clk can be driven at 1GHz for faster simulation times. |
| i_reset | Active high reset, synchronous to i_clk clock. Note: For designs that use FGT PMAs, you can monitor the status of the refclk_fgt_enabled_i port of the F-Tile Reference and System PLL Clocks IP and assert this signal if the FGT PMA reference clock is ever interrupted.
In general, for any cases when the F-Tile AN/LT IP must be reset while in operation, please follow the sequence below:
|
| Name | Width | Description |
|---|---|---|
| i_kr_reconfig_addr[11:0] | 12 | Address bus for auto-negotiation and link training control and
status registers (AN/LT CSRs).
|
| i_kr_reconfig_read | 1 | Read enable for AN/LT CSRs. |
| i_kr_reconfig_write | 1 | Write enable for AN/LT CSRs. |
| i_kr_reconfig_byte_en[3:0] | 4 | AN/LT byte enable signal for writing data. |
| i_kr_reconfig_writedata[31:0] | 32 | Write data for AN/LT CSRs. |
| o_kr_reconfig_readdata[31:0] | 32 | Read data from AN/LT CSRs. |
| o_kr_reconfig_readdata_valid | 1 | Valid signal for AN/LT CSRs read data. When asserted, the register is valid. |
| o_kr_reconfig_waitrequest | 1 | Indicates that the Avalon® memory-mapped interface is busy. The read or write cycle is only complete when this signal goes low. |
| Name | Width | Description |
|---|---|---|
| anlt_link | [NUMPORTS_GUI-1:0] | Used to connect to NUMPORTS_GUI Ethernet IP Instances. You must connect the port to the anlt_link port of the F-Tile Ethernet Hard IP. Note: This is a virtual wire that carries no signal information used by the
Quartus® Prime Tile Logic Generation flow to correctly connect the AN/LT IP to the Ethernet IP.
|
| port_state | [NUMPORTS_GUI-1:0] | Available only when you select Enable Dynamic AN/LT.
|