5.1. Clock Connections in Single Instance Operation - This clock connection describes a single IP core instantiation in your design. - 2026-01-06

F-Tile Ethernet Hard IP User Guide

This clock connection describes a single IP core instantiation in your design.

This is a typical clock connection requirement in a single IP core.

You must make the following clock connections:

The i_clk_ref and the i_clk_sys clocks drive the IP core.
The output clock o_clk_pll drives both the i_clk_rx and the i_clk_tx input signals.

Figure 22. Typical Clock ConnectionsThis diagram displays single Ethernet IP core and its related clock signals.

Table 27. Port Connection Guidelines between F-Tile Auto-Negotiation and Link Training for Ethernet IP and F-Tile Ethernet Hard IP
F-Tile Auto-Negotiation and Link Training for Ethernet IP	F-Tile Ethernet Hard IP
System PLL
`out_systempll_clk`	`i_clk_sys`
FGT
`out_refclk_fgt`	`i_clk_ref`
FHT
`out_fht_cmmpll_clk`	`i_clk_ref`